This application claims priority from Korean Patent Application No. 2001-65962, filed on Oct. 25, 2001, the contents of which are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates generally to the field of semiconductor devices and, more particularly, to a semiconductor chip package having a thermal interface material (TIM).
2. Description of the Related Art
Wire bonding is typically used to make electrical connections between a central processing unit (CPU) and chip Input/Outputs (I/Os) (e.g., the inner leads of semiconductor packages). Flip-chip technologies have been employed to package high-speed semiconductor devices. There are two types of semiconductor package structures formed using the flip-chip technologies; a lid type and a non-lid type. The lid type structure is typically used in chip packages that include a high-frequency CPU chip that generates large quantity of heat. The non-lid type structure is generally used in chip packages that have a low-frequency CPU chip that generates a relatively small quantity of heat.
FIGS. 1 and 2 show a conventional semiconductor chip package 100 having a lid 40. Electrode bumps 24 of a CPU chip 20 are attached to the upper surface 12 of a substrate 10 using flip-chip technology. The CPU chip 20 is covered with a lid 40. A plurality of external connection pins 30, electrically connected to the CPU chip 20, extend from a lower surface of the substrate 10. An epoxy resin 52 is formed between the CPU chip 20 and the substrate 10 as an underfill adhesive.
The lid 40 is made of a material having a good heat emissive capacity. In order to maximize the heat emissive capacity through the lid 40, a thermal interface material (TIM) 60 is interposed between a bottom surface 42 of the lid 40 and a back surface of the CPU chip 20. A non-conductive adhesive 54 (e.g., a non-conductive thermosetting silicone adhesive) is used as a sealant for attaching the lid 40 to the upper surface 12 of the substrate 10. After applying the non-conductive adhesive 54 to the perimeter of the substrate 10, the lid 40 is attached, and the non-conductive adhesive 54 is cured (hardened). Thus, the space on which the CPU chip 20 is mounted is encapsulated.
The TIM 60 can be a thermal grease type material or a rigid type material (such as epoxy or solder). The thermal grease type has a thermal conductivity of 1 to 6 W/mk. Epoxy has a thermal conductivity of 10 to 25 W/mk. Solder has a thermal conductivity of 25 to 80 W/mk.
In a conventional semiconductor package 100, the TIM 60 is arranged between the lid 40 and the CPU chip 20. In this arrangement, damage may occur depending on the type of TIM 60 used. For example, thermomechanical stresses arise due to differences in the coefficients of thermal expansion (CTE) between the lid 40, the CPU chip 20 and TIM 60. These CTE differences are commonly referred to as a xe2x80x9cCTE mismatch.xe2x80x9d Although the thermal grease type TIM does a good job of absorbing thermomechanical stresses between the lid 40 and the CPU chip 20, it has a poor heat emissive capacity. The rigid type TIM, such as solder, however, has a good heat emissive capacity, but is not capable of sufficiently absorbing the thermomechanical stresses between the lid 40 and the CPU chip 20. As a result, cracks occur in the rigid type TIM 60 itself or in the CPU chip 20.
Accordingly, there is a need for a semiconductor package that uses a solder or other material having a good heat emissive capacity as a thermal interface material and has an improved structure for absorbing thermomechanical stress.
The present invention provides a semiconductor package having voids formed in the thermal interface material (TIM), e.g., solder. The voids reduce the thermomechanical stresses to prevent the cracks of chip as well as those of the TIM.
The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A TIM is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.
According to one embodiment of the present invention, a plurality of void pads, formed of a material non-wettable by the TIM, e.g., solder, are arranged on the back surface of the chip. A copper pattern layer is formed on the back surface of the chip. The void pads are left exposed on the back surface of the chip. A nickel/gold plating layer is formed on the copper pattern layer. The voids are aligned with the plurality of void pads.
According to one aspect of the present invention, a solvent contained in a flux is volatilized to generate a gas during the reflow of the solder located between the lid and the chip. The gas concentrates on the void pads, thus forming voids having a predetermined size.